Hamid Savoj, Envis VP Engineering:

• Clock gating is one of the most popular and most utilized of low power techniques, and is powerful with very few unacceptable consequences downstream in terms of timing, area, and design complexity. Especially compared with voltage islands, power shutoff, dynamic frequency and voltage scaling, etc. However, and happily, the power reduction capabilities for clock gating have not been completely realized even in today’s flows. More reduction benefits are possible from clock gating, both combinational and sequential. Verification needs to change to reflect emerging technology in sequential clock gating.
• CPF and UPF have allowed easier implementation for voltage islands and power shutoff to address leakage. Vis-a-vis voltage scaling, there will be many new ideas on how voltage scaling can be addressed without additional design complexity, and in the face of increased process variability.
• EDA vendors must address the stated need for designers to look at low power holistically, including the software; considering all aspects of an embedded system, hardware and software, all considered together.

Holly Stump, Envis VP Marketing:

• The “ghost in the machine” for low power SoC design is: the temporal aspect! Software and stimulus, with the acknowledgement that there are many modes of operation for ICs in today’s convergent products.  We have done so much work on the hardware aspects: clock gating, voltage islands, power shutoff, dynamic voltage/frequency scaling, etc. We architect, we optimize and we measure. But based on what stimulus? The architectural power intent decisions must be made in the context of software. What modes of operation are most critical for the success of the product? Leakage or active power? Meaningful optimization depends on the mode of operation, the vectors,  the tie to actual software. For hardware designers, the grail is to really understand the software power profile. And often software developers do not have an easy way to take advantage of the power reduction techniques provided on-chip. This is a critical frontier.
• Adaptive voltage scaling is a technique that may revolutionize how companies provide, bin, and sell parts, not just SoC design practices. As adaptive voltage scaling becomes more mainstream, it will help recapture margins and silicon “goodness” especially as we move to more advanced process nodes. Challenges exist: partitioning for adaptive voltage zones and the concomitant power distribution  complexity; voltage regulators, on-chip or off, their efficiency profiles and design complexity especially at small geometries; and synchronization at a system level. However, the wave of the future may depend on our ability to dynamically compensate for variability in self-intelligent hardware design flows.
• Many design houses have been vocal at Q4 2008 shows such as the Embedded Power Conference, Portable Design, and the Power Forward Low-Power Summit, as well as privately with their low power roadmaps, confirming that the ability to predict the physical (timing, area, complexity) consequences of power design decisions earlier in the design flow is essential to rational low power architecture decisions.
• Power reduction for FPGAs is an exciting opportunity for both EDA and FPGA companies. The need, and the number of design starts, for low power FPGAs is growing, especially compared to SoC design starts. How can we apply the advanced low power techniques and knowledge from SoC designs to the benefit of FPGAs? New architectures, new flows, and new software layers are clearly indicated