Envis Slideshow: DAC 2008

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Automated Power Reduction for SoC Design

Do You Compete on Power?

What Does Power Cost You?

  • IC packaging
    • Higher package costs
    • Heat sinks
  • System cooling expense
  • Yield and reliability
    • Temperature failures
    • SI and DVD drop issues, metal migration
  • Die size and complexity
    • Overdesigned power grids increase die area and cost
    • Unnecessary timing closure problems
  • Time to market delay

Chill

  • Chill: next-generation clock gating
    • For designers of power sensitive SoCs who need to reduce power quickly and reliably
  • Reduces dynamic power
    • Up to 60% from original design
    • Up to 30% from manually clock-gated designs
  • Automated
    • Saves weeks or months of expert effort
    • Runs rapidly
  • Reduces area, reducing static (leakage) power
    • Up to 10% reduction from original design
    • No area/power tradeoff required

Automated Power Reduction

Design Power reduction Area reduction
Cell phone receiver 9% 18%
Wishbone IP core 15% 12%
USB controller 24% 3%
Encryption encoder 4% 19%
Memory controller 11% 3%
MPU 28% 2%

Chill: next-generation clock gating automates power reduction

  • Reduces dynamic power by up to 30% 
  • Often reduces leakage (and chip area) by up to 10%
  • Automates manual effort and expertise
  • Supports existing RTL to GDSII design methodologies

Kelvin Automated Power Pattern Generation (APPG)

  • For designers of power sensitive SoCs who need realistic power measurement
  • Automatically creates full coverage vectors specifically tuned for power measurement
  • Kelvin APPG is specific for power with superior QoR

Measuring Power Realistically

 

 Spreadsheet or guess Vectorless (Static) APPG Functional Simulation VCD
Approach Manual Probablistic Models clock and sequential behavior accurately Manual
Accuracy Inaccurate especially for process migration Inaccurate Accurate Unrealistic, over-exercise the design, corner cases
Design Knowledge Required Some required Not required Required, need global understanding
Time to develop Medium Short Short Difficult for complex designs
Time to run Short Short Short Long
Risk High High Low High, error-prone (human factor)

Kelvin Applications

  • For front end SoC designers who need accurate APPG and power estimates
  • For implementation teams who need power information and lack test vectors and/ or design knowledge
  • For designers using IP who need to validate power estimates from the IP vendor
  • For design services companies with customers who care about power

Perfect Fit in Existing Methodologies

Chill/Kelvin Methodology:

  • Run Kelvin and power estimation post-synthesis to get baseline power
  • Run Chill for power reduction Power optimization is vector-independent
  • Run Kelvin and power estimation after Chill to measure power savings
  • Run Kelvin after physical design for final signoff power including parasitics

“Envis’ products have enabled us to significantly lower our power consumption. Other alternatives, including the design techniques performed manually, do not provide the same level of power savings. ”

Chris Brown, Director of Digital Design, Amalfi Semiconductor

"In our partnership with Envis, we have collaborated on a solution that addresses power consumption and area reduction."

Tuan Nguyen, VO of Engineering, Amalfi Semiconductor

Come View The Envis Demo!

Automated Power Reduction
Next Generation Clock-Gating

  • Reduces dynamic power by 30-60% with no increase in area
  • Complements existing RTL to GDSII flows

Automatic Power Pattern Generation APPG

  • Automatically generates power vectors
  • Value throughout the design cycle for power measurement